1. Field of the Invention
The present invention relates to a quartz crystal oscillator which has a quartz crystal element and an IC chip having an oscillation circuit using the crystal element, both of which are contained in a surface mount package, and more particularly, to a crystal oscillator which uses a package body having an H-shaped cross-section with recesses in both main surfaces thereof and can securely connect an IC chip to the bottom surface of the recess.
2. Description of the Related Art
Surface mount type crystal oscillators are characterized by small size and light weight, and among others, temperature compensated crystal oscillators, which incorporate a temperature compensation mechanism for compensating a crystal element for frequency-temperature characteristics, are characterized by high frequency stability to variations in temperature. The surface mount type crystal oscillators are widely used as reference sources for frequency and time particularly in portable electronic devices including portable telephones and the like. In recent years, with an ever advancing reduction in size of surface mount type crystal oscillators, they are required to provide higher reliability.
FIG. 1A is a cross-sectional view illustrating an exemplary configuration of a conventional surface mount type crystal oscillator. The illustrated crystal oscillator comprises package body 1, quartz crystal blank 2, and IC (integrated circuit) chip 3. Package body 1 has a flat and substantially rectangular outer shape, and is formed with recesses in its top surface and bottom surface, respectively, resulting in an H-shaped cross section. Package body 1 is formed of laminated ceramic including flat and substantially rectangular central layer 1a, and upper and lower frame walls 1b, 1c each laminated to central layer 1a. Each frame layer 1b, 1c is formed in the shape of a frame which has a wall portion corresponding to an outer peripheral portion of central layer 1a, and an opening surrounded by the wall section. First recess 20a is formed by central layer 1a and upper frame layer 1b, as viewed in FIG. 1A, for receiving crystal blank 2 which functions as a crystal element. Second recess 20b is formed of central layer 1a and lower frame layer 1c, as viewed in FIG. 1A, for receiving IC chip 3 which contains the oscillation circuit and the like. Central layer 1a is comprised of first layer A, positioned on the upper side as viewed in FIG. 1A, and second layer B, positioned on the lower side as viewed in FIG. 1B, laminated on first layer A, thus causing the upper surface of first layer A to expose as the bottom surface of first recess 20a, and the lower surface of second layer B to expose as the bottom surface of second recess 20b. 
At four corners on the outer bottom surface of package body 1, i.e., at four corners on the lower surface of frame layer 1c, mounting electrodes 10 are respectively formed for use in surface-mounting the crystal oscillator on a wiring board. These four mounting electrodes are used, for example, as a power supply terminal, a ground terminal, an output terminal in which an oscillation output appear, and an AFC terminal which is applied with an AFC (automatic frequency control) signal. Though not shown herein, each mounting electrode 10 is formed to partially extend to the outer side surface of package body 1. The part of mounting electrode 10 formed on the outer side surface of package body 1 is called a “side electrode.” FIG. 1B is a bottom view of the crystal oscillator when IC chip 3 has not been mounted therein, better showing the positioning of mounting electrodes 10 and the bottom surface of second recess 20b. 
A plurality of circuit terminals 9 are disposed on the bottom surface of second recess 20b, i.e., on the lower surface of second layer B so that the circuit terminals are arranged along both long sides of central layer 1a. Circuit terminals 9 are provided in correspondence to IC terminals, later described, associated with IC chip 3. In the illustrated crystal oscillator, four circuit terminals 9 are arranged in a line along each long side. Four of these circuit terminals are electrically connected to the aforementioned four mounting electrodes 10, respectively, through conductive paths, not shown, formed on the bottom surface of second recess 20b. A pair of crystal test terminals X1, X2 are disposed in a central area on the bottom surface of second recess 20b, where crystal test terminals X1, X2 are electrically connected to a pair of crystal circuit terminals 9a, 9b among circuit terminals 9 through wiring paths 6 on the bottom surface of recess 20b. At the positions of crystal test terminals X1, X2, via-holes 8a, 8b are formed as electrode through-holes so as to extend through second layer B. Via-holes 8a, 8b are electrically connected directly to crystal test terminals X1, X2, respectively.
Crystal blank 2, which comprises, for example, a substantially rectangular AT-cut quartz crystal blank, is formed with excitation electrodes on both main surfaces thereof, respectively. From a pair of excitation electrodes, lead-out electrodes are extended toward both ends of one side of crystal blank 2, respectively. A pair of crystal holding terminals 4a, 4b are disposed on the bottom surface of first recess 20a, i.e., on the surface of first layer A. Crystal blank 2 is secured to and held in first recess 20a by securing these lead-out electrodes to crystal holding terminals 4a, 4b, for example, with conductive adhesive 11 at the positions from which the pair of lead-out electrodes are drawn.
A metal ring or metal thick film, not shown, is formed on the upper surface of frame layer 1b, such that metal cover 12 is bonded to this metal ring or the like to close first recess 20a, thereby hermetically sealing crystal blank 2 in first recess 20a. In this connection, metal cover 12 is electrically connected to the ground terminal among mounting electrodes 10 through a conductive path such as a via-hole, not shown.
On the upper surface of first layer A in substantially rectangular central layer 1a, the aforementioned crystal holding terminals 4a, 4b are disposed respectively in close proximity to both ends of one short side of first layer A, as illustrated in FIG. 2A. Via-holes 5a, 5b are also formed through first layer A in close proximity to the centers of both short sides of first layer A, respectively, as electrode through-holes. Crystal holding terminals 4a, 4b are electrically connected to via-holes 5a, 5b, respectively, through wiring paths 6 formed on the upper surface of first layer A.
FIG. 2B is a plan view illustrating the surface of second layer B which opposes first layer A, showing the layout of a conductor pattern on a laminated surface of second layer B with first layer A. As illustrated, shield electrode 7 is disposed substantially across the entire laminated surface of second layer B with first layer A. The entire outer periphery of shield electrode 7 extends to positions at which frame layers 1b, 1 c are formed, with the result that shield electrode 7 extends substantially below the entirety of first and second recesses 20a, 20b. Shield electrode 7 is partially cut out in a central area thereof, where a wiring path 6 is formed for connecting via-hole 5a to via-hole 8a, and another wiring path 6 is formed for connecting via-hole 5b to via-hole 8b. These via-holes 5a, 5b, 8a, 8b and wiring paths 6 are electrically independent of shield electrode 7. Shield electrode 7 is electrically connected to the ground terminal among mounting electrodes 10 through a conductive path such as a via-hole, not shown.
IC chip 3, which is substantially rectangular in shape, has an oscillation circuit using crystal blank 2 integrated on a semiconductor substrate. In addition to the oscillation circuit, a temperature compensation mechanism may be integrated on IC chip 3 for compensating crystal blank 2 for frequency-temperature characteristics. Since the oscillation circuit and the like are formed on one main surface of the semiconductor substrate through a general semiconductor device fabricating process, a circuit forming surface will refer to one of the two main surfaces of IC chip 3 on which the oscillator circuit and the like are formed. A plurality of IC terminals are disposed on the circuit forming surface along both long sides thereof. The IC terminals correspond to circuit terminals 9, 9a, 9b which are disposed on the lower surface of second layer B in central layer 1a, and are electrically connected to a circuit in IC chip 3. IC terminals include a pair of crystal connection terminals corresponding to crystal circuit terminals 9a, 9b, a power supply terminal, an output terminal, a ground terminal, and an AFC terminal, and further include write terminals for writing temperature compensation data into a temperature compensation mechanism in the case of a temperature compensated crystal oscillator. IC chip 3 is secured to the bottom surface of second recess 20b by bonding its IC terminals to circuit terminals 9, 9a, 9b disposed on the bottom surface of second recess 20b through ultrasonic thermo-compression bonding using bumps 13 by a so-called flip-chip bonding approach. Terminals corresponding to the write terminals, among circuit terminals 9, are electrically connected to write surface terminals 14 disposed on the outer side surface of package body 1 through conductive paths, not shown.
In this crystal oscillator, crystal holding terminals 4a, 4b are electrically connected to crystal test terminals X1, X2, respectively, through crank-shaped conductive paths including via-holes 5a, 5b, 8a, 8b formed at different positions of first layer A and second layer B in the central layer, and wiring paths 6 routed on the laminated surface of second layer B with first layer A. In this configuration, leaky hermetic sealing is prevented to ensure that first recess 20a is hermetically sealed, as compared with electrode through-holes which are formed through first layer A and second layer B by creating via-holes at the same positions of these layers. In addition, crystal blank 2 is prevented from being electrically coupled to IC chip 3 by shield electrode 7 formed on the laminated surface of first layer A with second layer B, thus maintaining good oscillation characteristics. Via-holes 5a, 5b, 8a, 8b are formed at positions at which they are covered with IC chip 3 when it is secured to second recess 20b. 
It should noted that crystal test terminals X1, X2 are provided for measuring oscillation characteristics of crystal blank 2 alone, for example, a crystal impedance (CI) and the like, as a crystal element, after crystal blank 2 is covered with metal cover 12 for hermetic sealing and before IC chip 3 is mounted in a crystal oscillator manufacturing process. By measuring the oscillation characteristics of crystal blank 2 before IC chip 3 is mounted, defective items can be eliminated to prevent defective oscillations after shipment caused by the crystal element.
After IC chip 3 has been secured to second recess 20b in the aforementioned manner, a protective resin is generally coated on second recess 20b as a so-called under fill for protecting the circuit forming surface of IC chip 3.
However, the surface mount type crystal oscillator configured as described above has a problem of defective connections of IC chip 3 with circuit terminals 9, 9a, 9b through bumps 13, caused by via-holes 5a, 5b, 8a, 8b formed electrically independently of shield electrode 7 in a central area of the laminated surface of second layer B with first layer A, on which shield electrode 7 is disposed, i.e., an area which is to be covered with IC chip 3.
Package body 1 is formed by laminating unburned ceramic sheets (green ceramic sheets), which are to be first layer A, second layer B and frame layers 1b, 1c, respectively, and burning these layers together. In this event, for forming circuit patterns including shield electrode 7 and via-holes 5a, 5b, 8a, 8b, conductor patterns of tungsten (W) or molybdenum (Mo) are printed as underlying electrodes on the unburned ceramic sheets before they are laminated, and after laminating and burning, a nickel (Ni) layer and a gold (Au) layer, for example, are sequentially formed following the conductor pattern by plating. However, the conductor pattern formed on the laminated surface of second layer B with first layer A is not plated and is therefore comprised only of the underlying electrode.
In this event, as illustrated in FIG. 3A, shield electrode 7 and via-holes 5a, 5b are formed separately from each other on the upper surface of first layer A in central layer 1a, resulting in an area between them in which no conductor pattern is formed. If second layer B is laminated on first layer A in such a situation, the surface of second layer B becomes curved due to outer peripheral electrodes P of via-holes 5a, 5b (and via-holes 8a, 8b) and shield electrode 7, which cause ruggedness equal to their thicknesses. It should be noted that FIG. 3A is drawn upside down with respect to FIG. 1A for the sake of description. Since the electrodes have thicknesses, for example, in a range of approximately 10 to 15 μm, level difference d due to the ruggedness formed on the surface of second layer B is equal to or larger than such thicknesses.
Thus, due to the ruggedness of second layer B which constitutes the bottom surface of the recess on which IC chip 3 is to be secured, as illustrated in FIG. 3B, bumps 13 may not be sufficiently compression-bonded to possibly cause defective connections at locations where the ruggedness create large gaps between second layer B and IC chip 3, when IC chip 3 is secured through thermo-compression bonding. For reference, the bottom surface of the recess is required to exhibit a flatness of 10 to 15 μm, which is similar to the thickness of the electrodes, during the thermo-compression bonding.